Shift register systems



Nov. l0, 1964 AyJ. KLINE, JR

SHIFT REGISTER SYSTEMS Original Filed Feb. 27, 1957 4 Sheets-Sheet 1INVENTOR. ARTHUR J. KLmt-,J

Y BY M Nov. 10, 1964 A. J. KLINE, JR

SHIFT REGISTER SYSTEMS Original Filed Feb. 27, 1957 4 Sheets-Sheet 2fINVENTOR.l ARTHUR .1. KLINQJR BY Ik.. :.k

TToRNf Y REGISI'ER. SYSFEEMSS Crignai Filed Feb. 1957' ARTHUR l.KLINlgJ,

IN V EN TOR.

BY Z

Nov. 10, 1964 A. .1. KLINE, JR

SHIFT REGISTER SYSTEMS Original Filed Feb. 27, 1957 4 Sheets-Sheet 4 wksmuv GS INVENTOR. ARTHUR J. Kum-,112. BY

Twmvfy United States Patent O 3,156,901 SHlFI' REGISTER SYSTEMS ArthurIl. Kline, Jr., Phoenix, Ariz., assigner to Radlo Corporation ofAmerica, a corporation of Delaware Continuation of application Ser. No.642,888, Feb. 27, 1957. This application Dec. 29, '1960, Ser. No. 79,4607 Claims. (El. 340-173) This is a continuation of co-pendingapplication, Serial No. 642,888, filed February 27, 1957, and assignedto the same assignee.

This invention relates to electronic shift registers, and particularlyto shift register systems for providing certain counting ratios.

In certain shift register systems, a shift register is connected to haveits tinal stage recirculate signals to its rst stage. Thereby, forexample, a ring counter may be formed to provide a counting ratiocorresponding to the number of shift register stages.

It is among the objects of this invention to provide:

A new and improved shift register system;

A new and improved shift register system for affording certain countingratios;

A new and improved shift register system for producing certain pulsepatterns.

In accordance with this invention, a shift register system is arrangedto recirculate pulses to the first stage from a plurality of otherstages. 'Ihe shift register may be filled and then emptied in accordancewith input pulses that are received. This system may be used, for eX-ample, to provide a counting ratio that is greater than the number ofregister stages.

The foregoing and other objects, the advantages and novel features ofthis invention, as well as the invention itself both as to itsorganization and mode of operation, may be best understood from thefollowing description when read in connection with the accompanyingrawing, in which like reference numerals refer to like parts, and inwhich:

FIGURE l is a block diagram of a shift register system embodying thisinvention;

FIGURE 2 is an idealized graph of the time relationships of certainoperations occurring at certain portions of the system of FIGURE 1;

FIGURE 3 is a schematic diagram of a magnetic core shift register systemembodying this invention;

FIGURE 4 is an idealized graph of waveforms occurring at certainportions of the system of FIGURE 2;

FIGURE 5 is a schematic diagram of another magnetic core shift registersystem embodying this invention; and

FIGURE 6 is a schematic diagram of another magnetic core shift registersystem embodying this invention for producing certain pulse patterns.

In the system of FEGURE 1, four stages 1i), 12, 14, and 16 of a binaryshift register are connected in series, the rst stage 1t) beingconnected to the second stage 12, the second stage 12 being connected tothe third stage 14, and so on. 'I'he shift register 13 may be of varioustypes, such as magnetic-core shift registers or vacuum-tube shiftregisters. Suitable shift registers of the vacuum-tube type, in whicheach stage is an Eccles- Jordan ip-op circuit, or bistable element, aredescribed in the book Automatic Digital Calculators by Booth and Booth,1953, starting at page 103. In such a vacuum tube shift register, thebinary state of each flipice flop stage is transferred to the succeedingstage upon the application of a shift pulse from a shift pulse generator2t). Thus, if the first stage 10 is in 'the l-state (or O-S'tate), thatl-state (or 0-state) is transferred to the second stage 12 upon theapplication of a shift pulse from the generator 2i). The shift pulseitself tends to drive the stages to the O-state. The same shift pulse isapplied unconditionally (i.e., without gating) to all of the stagessimultaneously, and the states of each stage are transferred to thesucceeding stage with the application of a shift pulse.

The output of the third stage 14 is connected to an input of an or gate22. Similarly, the output of the last stage lo is also connected to aninput of the or gate 22. The output of the or gate 22 is connected to aninput of a two-input and gate 2d. The output of the gate 24 is connectedto the input of the first stage 1t? of the shift register 1.3.

Each of the stages 10, 12, 1d and 16 is also provided with twoadditional outputs, a l-output and a (l-output. These 1- and O-outputsof each stage provide an enabling voltage level when the associatedstate is in the corresponding binary state, l or 0, and an inhibitingvoltage level when the associated flip-nop is in the reverse binarystate. The l-outputs of the stages il), 12, 14 and 16 are connected toinputs of a recognition gate, which gate 26 operates to recognize thecondition of all the stages being in the l-state. The O-outputs of thestages 1li, 12, 14 and 16 are applied to recognition gate 28, which gate28 recognizes the condition of ail the stages being in the O-state. Theshift pulse generator Ztl also supplies pulses to the gates 26 and Ztl.The gates 26 and 28 are coincidence gates that pass a shift pulse onlywhen they are enabled by all of their inputs.

The outputs of these gates 26 and 28 are respectively applied to thereset and set inputs of the nip-flop Sil via delay lines 33 and 32. Theoutput of the gate 2S is also applied to another input of the or gate22. The loutput of the flip-flop is applied to another input of the andgate 24%. This flip-iop output supplies an enabling and an inhibitingvoltage, respectively, when the tlip-tlop Si! is set and reset. A pulsesource 34 supplies a train of pulses to the generator Ztl. The generator2li supplies a shift pulse 36 in response to each pulse received fromthe source 34. The delay period of each delay line 32 and 33 is of theorder of the duration of a shift pulse 36.

The operation of the shift register system of FIGURE 1 is described withreference to the timing graph of FIGURE 2. Initially, the shift registerstages 1t), 12, 14 and 16 are all in the O-state, and the flip-nop 3G isreset. With this shift register condition, the recognition gate 2S is ina fully enabled condition due to enabling voltages from the O-outputs ofall the shift register stages. Accordingly, the first shift pulse 36 ispassed by gate 28. However, this passed pulse is blocked by the and gate24 which receives at that time an inhibiting voltage from the l-outputof the reset flip-flop 3i). This ipflop 3l) is set by the same shiftpulse 36 passed by the gate 28 after the delay of the delay circuit 32.Thus, after the first shift pulse 36, the shift register stages 16, 12,14 and 16 are still in the O-state, and the flip-flop 30 is set.

The second shift pulse 36 is again passed by the allzeros recognitiongate 2h and applied, via the or gate aise,

22, to the and gate 24. This pulse is passed by the gate 24 and drivesthe first stage l@ to the l-state. After the first stage it) is drivento the l-stage, the recognition gate 23 is closed.

The third shift pulse 36 advances the l-state from the first stage 1t)to the second stage 12, and the fourth shift pulse advances the l-statefrom the second stage 12 to the third stage 14. The fifth shift pulseadvances the lstate from the third stage 14 to the fourth stage 16, and,also, recirculates this l-state back to the first stage 1t) via the orgate 22 and the enabled and gate 24.

As shown in FIGURE 2, successive shift pulses after the fth advance thel-states to succeeding shift register stages and recirculate thisl-state to the hrst stage l@ from the third stage i4 and the fourthstage 1o. The eleventh shift pulse completes the filling of the shiftregister 18 by advancing the l-state from the third stage 14 to thefourth stage 16 and by recirculating this l-state back to the firststage Iii, so that all four stages are in the l-state. Under theseconditions, the all-ones recognition gate 26 is in the fuliy enabledcondition, and passes the next shift pulse 36 via the delay circuit 33to reset the iiip-iop Sil. Since the flip-flop 3i? is in the setcondition when this same shift pulse, the twelfth, is applied to theregister stages, the l-state is recirculated in the register 18, and allthe shift register stages are again in the l-state.

When the thirteenth shift pulse is applied, the ilip-flop 30 is reset,which reset condition closes the gate 24 to recirculation signals fromthe third and fourth shift register stages 14 and 15. Accordingly, thisthirteenth shift pulse serves t advance the l-State from each of theshift register stages 1u, 12 and 14 to the succeeding stages 12, 14 and16, respectively. However, due to the closed condition of the gate 24,the l-state of the third and fourth stages 14 and i6 is not recirculatedto the first stage 1b, and that first stage lil is changed to the-state. This operation is repeated with each succeeding shift pulse 25,the next such pulse 36 serving to advance the O-state of the first stage1t) to the succeeding stage, and so on. The sixteenth shift pulsechanges the fourth stage 16 to the O-state, and all the shift registerstages are then in the O-state. TheV allzeros recognition gate 23 is inthe fully enabled condition and open to the next shift pulse 36. Theseventeenth shift pulse finds the recognition gate 28 open and sets theflipiiop 36 to start a second full cycle. The operation described abovestarting with the first shift pulse is then repeated.

As may be seen from the Waveform graph of FIGURE 2, a complete cycle ofoperation is completed in sixteen shift pulses, and a new cycle isstarted on the seventeenth pulse. The pulse passed by the ali-zerosrecognition gate 2S to set the dip-flop 3u, or the setting of theflip-flop itself, may be used to mark the beginning of each cycle ofoperation. Such a pulse from the gate 2% (or the flipflop setting) maybe used to mark every sixteen pulses supplied from the source 34. It hasbeen found that the following formula may be used to determine thenumber o1 input or shift pulses that produce a complete cycle:(n-l)(np)-ln|q, where n is the number of stages in the recirculatingshift register, n-p is the order of stage from which the firstrecirculation takes place, and q is the number of pulses required torecognize the all-one and all-zero states and to perform the controloperations.

Thus, for the system of FIGURE 1, n-l is 3, n-p is 3, and q is equal tothe sum of 3 pulses and l pulse; that is, the sum of the three pulsesrequired to recognize the all- Axero state and have a first pulseentered into the shift register and the additional pulse, the twelfthshift pulse, occurring after the shift register has iilled, required torecognize this condition. Thus, this formula is consistent with thesixteenth pulse cycle in which the system of FIG- URE Vl operates. Inthis formula, the product term indicates the number of shift puises thatare required to fill the register from the O-state, the next term n isthe number of input pulses required to empty the register, and q thenumber of shift pulses required to perform the control operations.

In FIGURE 3, a shift register system similar to that of FIGURE l isshown in which magnetic cores are used as the shift register bistableelements. In FIGURE 3, a shift register 4t) includes the magnetic cores42, 44, 46 and 4S. Windings (not shown) on these cores are coupled fromcore to core by means of transfer circuits (not shown). The arrangementis such that the cores form a serial shift register from the first core42 to the last core 4S. A magnetic-core shift register of this type isdescribed in the article in the Proceedings of the IRE. of March 1955,entitled Logical and Control Functions Performed With Magnetic Cores, atpage 291. Symbols used in the system of FIGURE 3 are explained in somedetail in this article.

In the shift register 40, there is a recirculation connection back fromthe third stage 46 and from the fourth stage 4S to the first stage 42 ina manner similar to that described above with respect to FIGURE 1. Asuitable mixer or or gate (not Shown) is used to couple theserecirculation paths to the input of the core 42; such or gates (notshown) are used where required in other portions of the system of FIGURE3. The first core 42 also includes an inhibitory winding 50, indicatedby the slant bar through the core. This inhibitory winding, whenenergized, opposes the magnetizing effect of an input pulse received bythe same core.

Corresponding to each one of the shift register cores 42., 44, 46 and 48is a complement core 42', 44', 46' and 48', respectively. Inhibitoryinputs of the complement cores 42', 44', 46 and 4S receive the outputsvof the shift register cores 4Z, 44, 46, 48, respectively. Thesecomplement cores also receive inputs that are pulses from a pulsegenerator core 52. This pulse generator core 52 has a recirculationtransfer path from its output winding to its input Winding.

Two cores 54 and 56 are used to recognize the condition of all-ones inthe shift register 4t) and all-zeros in that register 4d, respectively.These cores receive as input pulses from the generator core 52. The core54 also receives as an inhibitory input the outputs of the complementcores 42', 44', 46', 48' mixed in an or gate (not shown). Similarly, thecore 56 receives as an inhibitory input the outputs of the registercores 4Z, 44, 45, 48 suitably mixed. Y

Two cores 58 and 60 are interconnected to form a flipiiop circuit 62.`These dip-flop cores 58 and et) have individual recirculation paths fromtheir output windings to their input windings. The output of therecognition core 54 is applied to the input ofthe core 58, and also tothe inhibitory input of the core 60. The output of the core 56 isapplied to the input of the core 60, to the inhibitory input of the core5S, and to the input of the first register stage 42. Signals applied tothe input of the core S8 are also applied to the inhibitory input Sti ofthe first register core 42 by way of the circuit connection 64. Shiftpulses are supplied by a generator 66; each shift pulse (SP.) is appliedsimultaneously and unconditionally to all the cores of the system ofFIGURE 3. Y

As initial operating conditions, the cores of the register 40 may all beset to the 0-state, and the complement cores 42', 44', 46', 48 set tothe l-state. The core 52 is set to the l-state, the cores 54, 56 settothe O-state, the core S8 set to the 1-state, and the core @il set tothe O-state. lSuitable windings (not shown) may be used on these coresfor setting these initial conditions.

The operation of the system of FIGURE 3 is described with reference tothe timing graph of FIGURE 4. The first shift pulse finds the dip-flop62 in the reset condition, that is, with the core 58 inthe l-state andthe core du in the 0-state. This first shift pulse drives the core S8 torecirculate a pulse, which recirculated pulse restores the core 58 tothe l-state. This recirculated pulse also appears at the fiip-fiopoutput connection 64 and is applied as an inhibitory input to the firststage core 42. The time relationship of these operations may be seen inthe waveform diagram of FIGURE 4 for the rst shift pulse. There are nooutput pulses from the register cores 42, 44, 46, 48, and there is anoutput pulse from each of the complement cores to the l-state.

This same first shift pulse does not produce an output pulse from therecognition cores 54 and 56, because these cores were initially in the(l-state. The output pulses from the complement cores inhibit a pulsefrom the generator core 52 applied to the recognition core S4, whichoperation results in the core 54 remaining in the O-state. However, theabsence of pulses from the register cores 42, 44, 46, 4S means there areno inhibitory pulses applied to the recognition core 56. Consequently,the pulse from the generator core 52 drives the recognition core S6 tothe l-state. This action of the coro 56 going to the l-State is arecognition of the allzero condition of the shift register cores 42, 44,46, 43. Thus, the first shift pulse results in the recognition of theall-zero condition of the shift register 4tlg otherwise, the circuitremains unchanged.

The second shift pulse produces generally the same operation in thesystem as that produced by the first shift pulse, except that theall-zeros recognition core 56 is driven from the 1-state to the O-stateto produce an output pulse at the connection 68. This pulse from thecore 56 is applied to the first register core 42 as an input; however,it is inhibited by the simultaneous application of an inhibitory pulsefrom the fiip-iiop output 64. This same pulse at the output 68 isapplied to the input of the core 60 to drive that core to the l-state,which action sets the iiip-flop 62. This same pulse at the output 63 isalso applied to the inhibitory input of the core 58 to inhibit theaction on that core 5S of the recirculated pulse applied to its input.With no output pulse from the register cores 42, 44, 46, 48, therecognition core 56 is again driven to the l-state by a pulse from thegenerator core 52. Thus, the effect of the second shift pulse is to setthe iiip-fiop 62; otherwise, the circuit rernains unchanged in itsconditions.

T he third shift pulse again produces a pulse at the output 6? of therecognition core 56. This pulse is applied to the input of the rstregister core 42. This pulse is applied to the input of the firstregister core 42, and, being uninhibited due to the absence of a puiseat the flip-flop output 64, this pulse drives the first register core 42to the l-state. This same pulse at the output 68 does not change thestate of the fiip-iiop 62. A pulse produced at the output of thehip-flop core 6d is applied to the inhibitory input of the recognitioncore 56 to inhibit the action of the pulse from the generator core S2;thereby, the core 56 remains in the O-state.

The fourth shift pulse changes the state of the first register core 42to produce an output pulse. This pulse from the core 42 is transferredto the core 44 to drive that core to the l-state. This same pulse fromthe core 42 is also applied as an inhibitory pulse to its complementcore 42 to prevent that core 42 from being driven to the l-state. Thissame pulse from the core 42 is applied as an inhibitory pulse to therecognition core 56, so that core 56 continues in the O-state. Thisfourth shift pulse finds the recognition core 56 in the -state, and nopulse is produced at the output 68.

The fifth shift pulse drives the second register core 44 to the (-stateto produce an output pulse, which is transferred to the third core 46 todrive that core 46 to the 1-state. This same pulse from the core 44 isapplied as an inhibitory pulse to the cores 44' and 56.

The sixth shift pulse drives the third core 46 to the 0-state to producea pulse that is transferred to the fourth stage core 48 to drive thatcore 4S to the l-state. This same puise from the core 46 is alsorecirculated back to 6 the first core 42 to drive that core to thel-state. The seventh shift pulse produces output pulses from the fourthcore 48 and from the first core 42. These pulses are respectivelytransferred to the first and second cores 42 and 44.

This operation continues for successive shift pulses, the 1states of thecores being transferred to the succeeding stage cores of the registerand also being recirculated back to the first core from the third andfourth cores 46 and 4S. The twelfth shift pulse (FIGURE 4) causes atransfer of a pulse from the first three register cores 42, 44, 46 tothe last three register cores 44, 46, 43, respectively, and therecirculation of the pulse from the third core 46 back to the rst core42. Thus, this twelfth shift pulse results in the register 40 beingfilled. This same twelfth shift pulse nds the complement core 46 in thel-state and produces an output pulse from that core 46', which pulseinhibits the all-ones recognition core 54. Due to the absence of anoutput pulse from the fourth register core 48, the fourth complementarycore 48 is driven to the l-state by a pulse from the generator core 52.

The thirteenth shift pulse nds all of the register cores 42, 44, 46, 48in the l-state, and produces output pulses from each one of these cores.However, this same thirteenth pulse finds the complementary core 48 inthe l-state, which results in an output pulse that inhibits therecognition core 54. Thus, the recognition core S4 is still in theO-state when the fourteenth. shift pulse is applied.

At the fourteenth shift pulse, all of the register cores 42, 44, 46, 48are in the l-state, and this pulse does not change that condition. Thissame fourteenth shift pulse finds all of the complement cores 42 44',46', 48 in the l-state, which results in a continuance of that conditionalso. No output pulse is produced from these comple ment cores and, as aresult, there is no inhibitory pulse applied to the recognition core S4.Accordingly, this core 54 is driven to the -state by a pulse from thegenerator core 52, which action is a recognition of the all-onescondition.

The fifteenth shift pulse produces the saine effects on the registerlcores and the complement cores as the preceding shift pulse. This samefifteenth pulse drives the recognition core 54 to the O-s-tate front thel-state to produce an output pulse at the connection '76. This pulse atthe connection 70 is applied to the input of the core 58 to drive thatcore 58 to the 1-state; thereby, the iiip-fiop 62 is reset. This samepulse at the output 7i) is also `applied to the connection 64 Itoinhibit the first stage core 42 to the register 46. This inhibitorypuise blocks recirculation to the first stage 42, and that first stageis left in the (iastate .at the end of the fifteenth shift pulse. Thesame pulse at the output 70 is applied to the inhibitory input of thecore 6th to inhibit the action of the recirculated pulse of that core661'.

The sixteenth shift pulse produces the transfer of the 0-state from 4thefirst core 42 to ythe second core 44. At the same time, the first core42 remains in the 0-state because any recirculation to that first core42 is inhibited by a pulse at the iiip-liop output 64.

The succeeding shift pulses produce similar results in the shiftregister 40, and the eighteenth shift pulse serves to shift the lastl-state from the fourth core 4S. Pulses from the flip-fiop output 64continue to inhibit input pulses :applied to the first core 42. The lastpulse read out from `the core 46 by ythe eighteenth shift puise inhibitsthe complement core 48'; otherwise, the condition of the system ofFIGURE 3 at the end of the eighteenth pulse is the same as the initialconditions described above that exist before the application of thefirst shift pulse. Thus, but for the absence of an output `pulse fromthe fourth complementing core 48', the operation produced by thenineteenth shift pulse is the same as that produced by the first shiftpulse. The twentieth shift pulse produces the same operation asaislar-ici the second shift pulse, the twenty-first the same as thethird, the twenty-.second the same as the fourth.

Thus, the shift register system of FIGURE 3 operates on an eighteenpulse cycle. The start of the cycle may be considered the generation ofan all-zero recognition pulse at the output 68 (or the setting of AtheHip-flop); each eighteen-pulse cycle being marked by two such pulses atthe output 65S (or by the flip-flop setting). r[his eighteen-pulse cycleis consistent with the formula noted above, in which the term n-l is 3,the term n-p is 3, land n is 4, and q is the sum of 2 land 3corresponding respectively to pulses required for the recognition ofall-ones and all-zeros.

In FIGURE 5, another embodiment of this invention is shown in whichthere are three recirculation paths in the shift register. The shiftregister of FIGURE includes seven cores 72, 74, 76, 78, titl, SZ and d4;the register connections are the same type as those of the register ofFIGURE 3. There is a recirculation connection 86 from the third stage 7ebach to the first stage V72, a recirculation connection 8.? from thefifth stage Si) back `to the first stage 72, and a recirculationconnection 9i) from the last stage back .to the lhst stage 72. Thecontrol circuitry described above with respect to FIGURE 3 may be usedin the system of FGURE 5 in a similar manner.

The operation of the system of FIGURE 5 is similar to that describedabove and will :be readily apparent from the above descriptions.Starting with the entry of the iirst pulse to the first core 72, twelvepulses `are required to till `the seven-core register. Once lil-led,seven pulses are required to empty the register; five pulses are needdeto perform .the recognition and control operations in .a manner similarto that described above with respect to FIGURE 3. Accordingly, `thesystem of FIG- URE 5 has a twenty-four pulse cycle.

It is seen from the above description that the principles of thisinvention are applicable to various types of shift registers; .thisinvention may be readily used with other types of magnetic core shiftregisters, and With shift registers using other types of binaryelements. This invention is applicable to shift registers havingdifferent numbers of stages and different numbers of recirculationpaths. The numbers and types of stages and recirculation paths aredetermined by considerations such as the counting cycle that is desired.

It has been found that, if the stages from which recirculation takesplace, that is, if the stages n and n P, have a ocmmon numerical factorother than unity, a complete pulse cycle in which the register is filledand then emptied, does not take place. Instead, after the register isonly partly filled, a stable condition is reached in which certainrecirculation pulse patterns and vregister conditions occur before theregister can till up. Such a shift register system is shown in FIGURE 6.

In FIGURE 6, a shift register system is shown that includes four cores92, 9d, 96, and 9%. rthere is a recirculation path from the second core9d back to the rst core, and a recirculation path back from the fourthcore 98 tothe rst core 92. It is seen that n and n-p have Vthe commonnumerical factor of 2.

Initially, a l-state is entered into the first core 9.2 by any suitablemeans, `such as by a pulse to the input connection 1%; that pulse is theonly signal supplied by means of :this connection Irllti. The firstshift pulse shifts the l-state to the second core 94. The second shiftpulse shifts the l-state 4to the third core X and recirculates thatl-state back to the first core 212. At the end of this Isecond shiftpulse, the pattern of binary conditions of the cores 92, 94, 96, 98 is1010, respectively. 'Ihe next shift pulse shifts these l-states .to thesucceeding cores so that the pattern of core conditions is 9101,respectively. The next shift pulse restores .the `core conditions to thePfr-Viens pattern of lOlO, respectivel.

Succeeding shift pulses produce these same pulse patterns alternately.

ln accordance with this invention, a new and improved shift registersystem is provided. This system may be used for affording certaincounting ratios, and for producing certain pulse patterns.

What is claimed is:

1. A shift register system comprising a shift register having aplurality of stages connected for series operation from a first stage toa last stage, each of said stages including a bistable element forstoring binary signals and means for applying simultaneous shift pulsesunconditionally to the bistable elements in all of said stages so thateach bistable element receives each shift pulse, said elements beingresponsive to said pulses to shift simultaneously the binary signalsstored in said register, and recirculation means connecting the bistableelements in a plurality of said stages' to the bistable element in saidfirst stage.

2. A shift register system comprising a shift register having aplurality of stages connected for series operation from a first stage toa last stage, each of said stages including a bistable element forstoring binary signals, and means for applyino simultaneous shift pulsesunconditionally to the bistable elements in all of said stages so thateach bistable element receives each shift pulse, said elements beingresponsive to said pulses to shift simultanously the binary signalsstored in said register, recirculation means connecting the bistableelements in a plurality of said stages to the binary element in saidfirst stage, and means responsive to a certain combination ofsignal-storing conditions of said elements for controlling therecirculation of signals.

3. A shift register system as recited in claim 2 Wherein saidcombination responsive means includes means responsive to onecombination of said conditions for preventing the recirculation ofsignals, and responsive to another combination of said conditions forenabling the recirculation of signals.

4. A shift register system comprising a shift register having aplurality of stages connected in order from a first stage to a laststage, each of said stages including a bistable element for storingbinary signals and means for applying simultaneous shift pulsesunconditionally to the bistable elements in all of said stages so thateach bistable element receives each shift pulse, said elements beingresponsive to'said pulses to shift simultaneously the binary signalsstored in said register, and having recirculation means connecting oneof said bistable elements to another of preceding order, and meansresponsive to a certain combination of signal-storing conditions of saidelements for controlling the recirculation of signals.

5. A shift register system as recited in claim 4 Wherein saidcombination responsive means includes means responsive to onecombination of said conditions for preventing the recirculation ofsignals, and responsive to another combination of said conditions forenabling the recirculation of signals.

6. A shift register system comprising a shift register having aplurality of stages, each of said stages including a bistable elementfor storing binary signals, said elements being connected for signalshift operation from each element to a succeeding order element, andmeans for applying simultaneous shift pulses unconditionally to thebistable elements in all of said stages so that each bistable elementreceives each shift pulse, said elements being responsive to said pulsesto shift simultaneously the signals stored in said register, saidregister also having a plurality of different recirculation means eachfor transfer of signals from one of said elements to a preceding orderelement.

7. A shift register system comprising a shift register having aplurality of stages, each of said stages including a bistable elementfor storing binary signals, said elements being serially connected forsignal shift operation 9 i9 from one element to a succeeding orderelement, and to another combination o said conditions for enabling meansfor applying simultaneous shift pulses uncondithe recirculation ofsignals. tionally `to the bistable elements in all of said stages, saidelements being responsive to said pulses to shift simul- ReferencesCited inthe le of this patent taneouslv the signals .stored iii saidregister, said register 5 UNlTED STATES PATENTS also having a pluralityof diterent recirculation means v each for transfer of signals from oneof said elements to 21652561 W11S0n Sept- 151 1953 a preceding orderelement, and means responsive to one 2,806,947 MacKmgh Sept 17, 1957combination of signal-storing conditions of said elements 2,853238Johnson SGP- 23, 1953 for preventing the recirculation of signals andresponsive 10 2,951,230 Caddel Aug. 30, 1960 UNITED STATES PATENT OFFICECERTIFICATE 0E CORRECTION Patent No. 3, 156,901 November lOq i964 ArthurJ Kline, JIM,

It is hereby certified that error appears in the above numbered patentrequiring correction and that the said Letters Patent should read ascorrected below.

Column 3Y line 72, for "sixteenth" read sixteen line 3 after "stages"insert so that each bistable element receives each shift pulse Signedand sealed this 13th day lof April 1965.

(SEAL) Attest:

ERNEST W. SWIDER EDWARD J. BRENNER Attesting Officer Commissioner ofPatents

1. A SHIFT REGISTER SYSTEM COMPRISING A SHIFT REGISTER HAVING APLURALITY OF STAGES CONNECTED FOR SERIES OPERATION FROM A FIRST STAGE TOA LAST STAGE, EACH OF SAID STAGES INCLUDING A BISTABLE ELEMENT FORSTORING BINARY SIGNALS AND MEANS FOR APPLYING SIMULTANEOUS SHIFT PULSESUNCONDITIONALLY TO THE BISTABLE ELEMENTS IN ALL OF SAID STAGES SO THATEACH BISTABLE ELEMENT RECEIVES EACH SHIFT PULSE, SAID ELEMENTS BEINGRESPONSIVE TO SAID PULSES TO SHIFT SIMULTANEOUSLY THE BINARY SIGNALSSTORED IN SAID REGISTER, AND RECIRCULATION MEANS CONNECTING THE BISTABLEELEMENTS IN A PLURALITY OF SAID STAGES TO THE BISTABLE ELEMENT IN SAIDFIRST STAGE.